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L6996
DINAMICALLY PROGRAMMABLE SYNCHRONOUS STEP DOWN CONTROLLER FOR MOBILE CPUs
s s s s s
s s s s s s s s s
5 BIT DAC WITH AVAILABLE EXTERNAL OUTPUT VOLTAGE. 0.6 TO 1.750V, DYNAMICALLY ADJUSTABLE OUTPUT VOLTAGE RANGE. 1% OUTPUT ACCURACY OVER LINE AND LOAD. ACTIVE DROOP. CONSTANT ON TIME TOPOLOGY ALLOWS LOW DUTY CYCLE AND FAST LOAD TRANSIENT. 90% EFFICIENCY FROM 12V TO 1.35V/8A. 1.750V TO 28V BATTERY INPUT RANGE. OPERATING FREQUENCY UP TO 1MHZ. INTEGRATED HIGH CURRENT DRIVERS. LATCHED OVP AND UVP PROTECTIONS. OCP PROTECTION. 350A TYP. QUIESCENT CURRENT. 7A TYP. SHUTDOWN SUPPLY CURRENT. PGOOD AND OVP SIGNALS. ZERO-CURRENT DETECTION AND PULSEFREQUENCY MODE.
TSSOP24 ORDERING NUMBERS: L6996D (TSSOP24) L6996DTR (Tape & Reel)
APPLICATIONS s ADVANCED MOBILE CPUs SUPPLY WITH DYNAMIC TRANSITIONS. s NOTEBOOK/LAPTOP, CONCEPT PC CPUs SUPPLY. s DC/DC FROM BATTERY SUPPLY EQUIPMENTS. APPLICATION DIAGRAM
5V
DESCRIPTION The device is dc-dc controller specifically designed to provide extremely high efficiency conversion for mobile advanced microprocessors. The "constant on-time" topology assures fast load transient response. The embedded "voltage feedforward" provides nearly constant switching frequency operation. A precise 5-bit DAC allows select output voltage from 0.6V to 1V with 25mV steps and from 1V to 1.75V with 50mV steps. L6996 is capable of supporting CPUs VID combination changing during normal operation. The active droop allows adjust both the output loadline slope and the zero-load output voltage.
25V
VCC
VDR
OSC BOOT HGATE HS
5V
L
PHASE PGOOD OVP
RSENSE
V OUT
1.25V
L6996
LGATE
LS
DS
ILIM
PGND GND CS+ CS-
SS
CSS
VFBVFB+
SHDN VID4:0
VPROG
CVPROG
July 2002
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L6996
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDR VCC to GND VDR to GND HGATE and BOOT, to PHASE HGATE and BOOT, to PGND VPHASE PHASE LGATE to PGND ILIM, VFB+, VFB-, CS-, CS+, SHDN, VID0-4, PGOOD, OVP, VPROG to GND Ptot Tj Tstg Maximum Power dissipation at Tamb = 25C Junction operating temperature range Storage temperature range Parameter Value -0.3 to 6 -0.3 to 6 -0.3 to 6 -0.3 to 36 -0.3 to 30 -0.3 to VDR+0.3 -0.3 to VCC+0.3 1 0 to 125 -55 to 125 Unit V V V V V V V W C C
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient Value 125 Unit C/ W
PIN CONNECTION
VID2 VID1 VID0 CSCS+ VCC GND VPROG VFB+ VFBOSC SS 1 2 3 4 5 6 7 8 9 10 11 12
TSSOP24
24 23 22 21 20 19 18 17 16 15 14 13
VID3 VID4 BOOT HGATE PHASE VDR LGATE PGND PGOOD OVP SHDN ILIM
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L6996
PIN FUNCTIONS
N 1,2,3, 23,24 4 5 6 7 8 9 Name VID4-0 CSCS+ VCC GND VPROG VFB+ Description Voltage Identification inputs. VID0 is the LSB and VID4 is the MSB for the DAC (see VID table) This pin is used for both current sensing and to detect overvoltage and undervoltage conditions. Current sense pin. Overcurrent condition is detected by sensing CS+ to CS- voltage. Supply voltage for analogy blocks. Connect it to 5V bus. Signal ground DAC output voltage. This pin provides the voltage programmed by the DAC. Connect a 10nF capacitor between this pin and GND. PWM comparator reference input. Connect this pin to VPROG. An additional external voltage divider between output and VPROG may be used to realize the active droop function. PWM comparator feedback input, to be connected to the regulated output. By inserting a resistor between this pin and the regulated output, a positive offset can be added to the output voltage. Connect this pin to the battery through a voltage divider in order to provide the voltage feedforward feature. Soft start pin. 5A constant current charges an external capacitor whose value sets the softstart time. An external resistor connected between this pin and GND sets the current limit threshold. ShutDown input. When connected to GND the device stops working. When high, it enables the IC operation. Open drain output. The pull-down transistor is off either in OV condition or during a VID transition. Open drain output. The pull-down transistor is on during soft-start, dynamic transitions and when an output voltage fault occurs. Power Ground. This pin has to be connected close to the low side MOSFET source in order to minimize switching noise. Lower MOSFET gate driver output. Voltage supply for the low side internal driver. This pin provides the return path of the high side driver. High side MOSFET driver output. Bootstrap capacitor pin. The high side driver is supplied through this pin.
10
VFB-
11 12 13 14 15 16 17 18 19 20 21 22
OSC SS ILIM SHDN OVP PGOOD PGND LGATE VDR PHASE HGATE BOOT
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ELECTRICAL CHARACTERISTICS (VCC = VDR = 5V; Tamb = 0C to 70C unless otherwise specified)
Symbol SUPPLY SECTION Vin Vcc, VDR Vccoff VHYST Iqcc (VDR) Iqcc (Vcc) SHDN ISH (VDR) Turn-off voltage UVLO Hysteresys Quiescent current driver Quiescent current VFB- > VFB+ VFB- > VFB+ Input voltage range Vout=1V Fsw=110Khz Iout=1A 1 4.5 4.1 60 90 28 5.5 4.3 100 20 600 V V V mV A A Parameter Test Condition Min. Typ. Max. Unit
SHUTDOWN SECTION SHDN Threshold Driver quiescent current in shutdown. SHDN to GND SHDN to GND 4 0.9 Vprog=CS- =1.15 Osc=250mV Vprog=CS-=1.15 Osc=500mV Vprog=CS-=1.15 Osc=1V Vprog=CS-=1.15 Osc=2V OFF TIME Minimum Off Time KOSC/TOFFMIN DAC Vprog Voltage Accuracy Input voltage offset IVFBILIM KC PHASEGND Input bias current (VP) ILIM input bias current Positive and negative Current Limit factor. Zero Crossing Comparator offset VID0-4 see table 1 V PROG=1.6V=VFBVVFB- =1.6V CS-=VPROG=1.6V ILIM to GND = 120K RILIM = 120 K 0.18 -2 -1 -2 4 5 4.95 0.3 0.24 2 +1 +2 6 % mV A A A mV PWM COMPARATOR OSC=250mV VPROG=CS-=1.15V 0.28 580 ns 720 355 210 120 800 420 250 150 880 485 290 180 0.6 1.2 5 15 6 V A A A V ns ns ns ns
ISH (Vcc) Shut down current SOFT START SECTION ISS ON TIME Ton On time duration SS charge current Soft-start active range
CURRENT LIMIT AND ZERO CURRENT COMPARATOR
GATE DRIVERS High side rise time High side fall time Low side rise time Low side fall time PROTECTIONS OVP Over voltage trip CS- rising 117 120 123 % VDR=5V; C=7nF HGATE - PHASE from 2 to 4.5V 50 50 50 50 70 70 70 70 ns ns ns ns
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ELECTRICAL CHARACTERISTICS (continued) (VCC = VDR = 5V; Tamb = 0C to 70C unless otherwise specified)
Symbol UVP PGOOD PGOOD Ron PGOOD Parameter Under voltage trip Upper threshold (CS-/VPROG) Lower threshold (CS-/VPROG) Test Condition CS- falling CS- rising; PGOOD active CS- falling; PGOOD active ISOURCE=2mA Min. 66 109 84 40 Typ. 69 112 87 60 Max. 72 115 90 100 Unit % % %
Table 1. DAC Output Voltage
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output Voltage (V) 0.600 0.625 0.650 0.675 0.700 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.050 1.100 1.150 1.200 1.250 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750
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VCC
FB-
-
Ton= Kosc V(CS-)/V(OSC)
S Q
pwm comparator
CS-
OSC
Ton= Kosc V(CS-)/V(OSC)
VID4:0 dynamic transition control PHASE + zero-cross comparator
dynamic transition detection 80 us one-shot
dynamic transition mode dynamic transition mode
5 bit DAC
bandgap
1.236V
+ +
CS+ CS0.05
negative current limit comparator
VPROG 1.416
ILIM
VID4:0 DAC configuration LS control
Reference chain
CS-
OSC
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5V
PGOOD VCC GND + CS1.12 VPROG undervoltage comparator CS0.6 VPROG IC enable pgood comparators + 1.075 VPROG CSCS0.925 VPROG HGATE BOOT V(LGATE)<0.5V comp LS and HS anti-cross-conduction comparators + soft-start control S R + OVP overvoltage comparator
L6996
SHDN
SS
5 uA
ILIM
power management
V IN
R Q V(PHASE)<0.2V comp PHASE level shifter HS driver
Figure 1. Functional & Block Diagram
Toff min delay S
V OUT
CS+ Ton min one-shot Q LS driver
positive current limit comparator VDR
+
CS-
-
0.05 R Ton one-shot
+ -
LGATE
FB+ S
PGND
+
Ton
one-shot
V IN
R
5 uA
HS control
OSC
L6996
TYPICAL OPERATING CHARACTERISTICS The test conditions refer to the component list the table 5. V IN = 20V V OUT = 1.8V FSW = 270kHz Tamb = 25C unless otherwise noted. Figure 2. Dynamic Output Voltage Transition 1.55V -> 1.35V Figure 5. Startup with Zero Load
CH1 -> VPHASE CH2 -> VOUT CH4 -> IL
CH1 -> VOUT CH2 -> SS CH3 -> IL
Figure 6. Startup with 10A Figure 3. Dynamic Output Voltage Transition 1.35V -> 1.55V
CH1 -> VOUT CH2 -> SS CH3 -> IL CH1 -> VPHASE CH2 -> VOUT CH4 -> IL
Figure 4. Load Transient 0-15A
CH1 -> VOUT CH2 -> VOUT CH4 -> IL
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Figure 7. Test Condition: Vin = 20V, V5v=5V, Fsw = 300kHz, Tamb = +25C
Efficency [%]
0.88 0.86 0.84 0.82 0.8
Vout=1.25 Vout=1.35 Vout=1.7
0.78 0.76 0.10 1.00
Current [A]
10.00
100.00
Figure 8. Test Condition: Vout = 1.75V, Fsw = 300kHz, V5v = 5V, Tamb = +25C
Efficency [%]
0.92 0.91 0.9 0.89 0.88 0.87 0.86 0.85 0.84 0.83 0.82 0.81 0.1 1.0 Vin=7
Vin=12
Vin=20
10.0
100.0
Current [A]
Figure 9. Test Condition: Vout = 1.75V, V5v = 5V, Tamb = +25C
Frequency [KHz]
410 390 370 350 330 310 290 270 250 4 5 6 7 8 9 10 11 12 13 14 15 Vin=20 Vin=12 Vin=7
Current [A]
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Figure 10. Typical Application with Active Voltage Droop
5V
CV51 RV5 RVIN1 RVIN2 CVIN1 CVIN2
V IN
VCC
CV52
OSC VDR BOOT HGATE
C
HS
D
BOOT
BOOT
RPU2
RPU1
PHASE PGOOD OVP LGATE LS
L
RSENSE
V OUT
RIL1
ILIM
L6996
DS
CPU COUT COUT1
PGND GND
RIL2 MIL
SS
CS+ CSVFBVFB+
CVP3 RVP1 RVP3 RVP2 CVP1
CSS
SHDN VID4:0
VPROG
CVPROG
Figure 11. Typical Application without Active Voltage Droop
5V
CV51 RV5 RVIN1 RVIN2 CVIN1 CVIN2
V IN
VCC
CV52
OSC VDR BOOT HGATE
C
HS
D
BOOT
BOOT
RPU2
RPU1
PHASE PGOOD OVP LGATE LS
L
RSENSE
V OUT
RIL1
ILIM
L6996
DS
CPU COUT COUT1
PGND GND
RIL2 MIL
SS
CS+ CSVFBVFB+
CSS
SHDN VID4:0
VPROG
CVPROG
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1 DEVICE DESCRIPTION
1.1 Constant On Time PWM Topology Figure 12. Loop block schematic diagram
Vin R1 One-shot generator OSC CSFFSR RQ HGATE S Q LS LGATE VID0-4 DS
R2
HS Rsense
Vout
DAC
Vprog
VFB+ VFB-
+ -PWM comparator
This device implements a Constant On Time control, where the Ton is the on time duration forced by a one-shot circuit. The controller calculates the one-shot time directly proportional to the V CS- pin voltage and inversely to the OSC pin voltage as in Eq 1: Eq 1 V CST O N = K O SC -------------- + V
OS C
where KOSC=180ns and is the internal propagation delay time (Typ. 40ns). The system imposes in steady state a minimum on time corresponding to V OSC = 2V. In fact if the VOSC voltage increases above 2V the corresponding Ton will not decrease. Connecting OSC pin to a voltage partition from VIN to GND, it allows steadystate switching frequency FSW independent of V IN. It results: Eq 2 where Eq 3 R2 V OS C O SC = -------------- = -------------------V IN R2 + R 1 V OUT 1 F SW = -------------- ---------- O SC = F SW K O SC V IN T O N
The above equations allow setting the frequency divider ratio aOSC once output voltage has been set; note that such equations hold only if VOSC<2.A minimum off-time constrain of about 500nS is introduced in order to assure the boot capacitor charge and to limit switching frequency after a load transient as well as to mask PWM comparator output against switching noise and spikes. The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three
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L6996
conditions are met contemporarily: the PWM comparator output is low (i.e. the output voltage is below the reference voltage), the minimum off time is passed and the current limit comparator is not triggered (i.e. the inductor current is under the current limit programmed value). The voltage on the OSC pin must range between 50mV and 2V to ensure the system linearity. 1.2 Closing the loop The loop is closed connecting the output voltage to the FB- pin. The FB- pin is linked internally to the comparator negative pin and the positive pin is connected to the programmed voltage as in Figure 12. When the FB- goes lower than FB+, the PWM comparator output goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise spike. After the on-time (calculated as described in the previous section) the system resets the flip-flop and then turns off the high side MOSFET and turns on the low side MOSFET. Internally the device has more complex logic than a flip-flop to manage the transition in correct way. For more details refers to the schematic Fig. 1. Because the system implements a valley loop control, the average output voltage is different from the programmed one as shown in figure 13. Figure 13. Valley Regulation
Vout
DC Error Offset

Vref
Time
Figure 14. Voltage positioning network
Rsense R4
To inductor
To Vout
PWM COMPARATOR
R1
+
VFBVFB+ Vprog
R2
R3
L6996
The L6996 performs an externally adjustable active droop, achieving a 4m V/A load line slope using a 1.5m sense resistor without use an external amplifier. Focusing the attention on the control part of the system (Figure 14), it can be considered that the inductor current can revert (the PFM function is deal towards) and the current
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L6996
has an average value equal to Io. The intention is to find the output average value called Vo. It is important to remember that the loop is closed a valley of the ripple, in this conditions the inputs of PWM comparator must be equal, so the VFB+ =VFB-. Suppose R4=0 and R3=open. Considering this and watching the figure 14 it can be written two equations at the VFB+ and VFB- node: Eq 4 Eq 5 Rsense * Io = Vc ( V ov alle y - V prog ) R1 ----------------------------------------------------------- = Vc R1 + R2
Imposing Eq4=Eq5 it can be found the VOVALLEY value: Eq 6 Vovalley = Vprog + Rs * (1 + R1/R2) * Io
Form Eq6 it can be noted the active drop effect due to R1, R2 resistors; it can be also noted the output average value is different from the VPROG value, the error is due to the valley control, and it is equal to half of the ESR voltage ripple. To reduce the error of the average output voltage we can change the VPROG value using resistors. In fact considering the R3 resistor we can make a Thevenin equivalent: Eq 7 Eq 8 Vprogeq = Vprog * R3/(R3 + R2) Req = R3//R2
How it can be seen the VPROGEQ is less the VPROG and so we can reduce the average output error. Remember that the R1, R2 and RSENSE are selected in base at the Voltage Positioning needs. The R4 resistor can be used to set also a positive offset at zero load. Considering the PWM comparator inputs: Eq 9 Vo = VFB+ + R4 * 5A
Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hysteretic system the frequency can change with some parameters (input voltage, output current). In L6996 is implemented the voltage feed-forward circuit that allows constant switching frequency during steady-sate operation with the input voltage variation. There are many factors affecting switching frequency accuracy in steady-state operation. Some of these are internal as dead times, which depend on high side MOSFET driver. Others related to the external components as high side MOSFET gate charge and gate resistance, voltage drops on supply and ground rails, low side and high side RDS ON and inductor parasitic resistance. During a positive load transient, (the output current increases), the converter switches at its maximum frequency (the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output current decreases), the device stops to switch (high side MOSFET remains off). 1.3 Transition from PWM to PFM To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM mode essentially for the off section; the on section is the same. In PFM after a turn-on cycle the system turnson the low side MOSFET, until the current reaches the zero A value, when the zero-crossing comparator turns off the low side MOSFET. In this way the energy stored in the output capacitor will not flow to ground, through the low side MOSFET, but it will flow to the load. In PWM mode, after a turn on cycle, the system keeps the low side MOSFET on until the next turn-on cycle, so the energy stored in the output capacitor will flow through the low side MOSFET to ground. The PFM mode is naturally implemented in hysteretic controller, in fact in PFM mode the system reads the output voltage with a comparator and then turns on the high side MOSFET when the output voltage goes down a reference value. The device works in discontinuous mode at light load and in
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L6996
continuous mode at high load. The transition from PFM to PWM occurs when load current is around half the inductor current ripple. This threshold value depends on VIN, L, and VOUT. Note that the higher the inductor value is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the transient response is. In PFM mode the frequency changes, with the output current changing, more than in PWM mode; in fact if the output current increase, the output voltage decreases more quickly; so the successive turn-on arrives before, increasing the switching frequency. The PFM waveforms may appear more noisy and asynchronous than normal operation, but this is normal behaviour mainly due to the very low load. The NOSKIP feature cannot be disabled. 1.4 Softstart If the supply voltages are already applied, the SHDN pin gives the start-up. The system starts with the high side MOSFET off and the low side MOSFET on. After the SHDN pin is turned on the SS pin voltage begins to increase and the system starts to switch. The softstart is realized by gradually increasing the current limit threshold to avoid output overvoltage. The active soft start range (where the output current limit increase linearly) starts from 0.6V to 1.5V. In this range an internal current source (5A typ) charges the capacitor on the SS pin. The reference current (for the current limit comparator) forced through ILIM pin is proportional to SS pin voltage and it saturates at 5A (typ.) when SS voltage is close to 1.5V; so the maximum current limit is active. Output protections like undervoltage is disabled until SS pin voltage reaches 1.5V, instead the overvoltage is always present. Once the SS pin voltage reaches the 1.5V value, the voltage on SS pin doesn't impact the system operation anymore. If the SHDN pin is turned on before the supplies, the correct start-up sequence is the following: first turn-on the power section and after the logic section (VCC pin). Figure 15. Soft-start diagram
Vss
4.1V 1.5V
Soft-start active range 0.6V
Ilim current
5A
Time
Maximum current limit
Time
1.5 Current limit The current limit comparator senses inductor current through the sense resistor when the low side MOSFET is on and compares this value with the ILIM pin voltage. While the current is above the prefixed value, the control inhibits the one-shot start. To properly set the current limit threshold, it should be noted that this is a valley current limit. Average current depends on the inductor value, VIN e VOUT. Eq 10 IOUTCL = IMAX_VALLEY + IL / 2
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To set the current threshold, choose R ILIM according to the following equation: Eq 11 R ILIM I M AX_VAL LEY = --------------------- K C R SENS E
Where KC is the current limit factor (0.25A typ.). A negative current limit is also introduced during dynamic transitions, when zero-cross comparator is disabled and at the inductor current is allowed to reverse. The negative current limit is useful when performing a negative transition (that is, output voltage is reduced) to avoid too high discharging current. Both positive and negative current limit have the same threshold; but the negative current limit can be set using the OVP signal plus a transistor, that changes during the dynamic transition, as in Fig. 16 (Q5, R11). The system accuracy is function of the exactness of the resistance connected to ILIM pin and RSENSE resistor. Moreover the voltage on ILIM pin must range between 10mV and 2V to ensure the system linearity. 1.6 Protection and fault Sensing CS- pin voltage performs the output protection. The nature of the fault (that is, latched OV or latched UV) is given by the PGOOD and OVP pins. If the output voltage is within the 90% 110% range, PGOOD is high. If an overvoltage or an undervoltage occurs, the device is latched. low side MOSFET is turned ON and high side MOSFET off. PGOOD goes low. OVP goes high in case of overvoltage, allowing the fault nature to be detected. To recuperate the functionality either the device must be shut down, thought the SHDN pin, or the supply has to be removed. These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV fault). 1.7 Drivers The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching transition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the voltage on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage reaches 500mV. This is important since the driver can work properly with a large range of external power MOSFETS. The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the root square of the MOSFET gate charge and the switching frequency. So the power dissipation of the device is function of the external power MOSFET gate charge and switching frequency. Eq 12 Pdriver = VCC * QgTOT * FSW
The maximum gate charge values for the low side and high side are given from: Eq 13 f SW0 Q M AXHS = ------------ 75 nC f SW
Eq 14
f SW 0 Q M AXLS = ------------ 125nC f SW
Where fSW0 = 500kHz. The equations above are valid for TJ = 150C. If the system temperature is lower the QG can be higher. For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;
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L6996
in this case the maximum value is QMAXLS = 125nC. The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect. 1.8 Digital to analog converter The built-in digital to analog converter (DAC) allows the adjustment of the output voltage in correspondence to the Table1 in pag 4: from 0.6V to 1V with 25mV steps, and from 1V to 1.75V with 50mV steps. The DAC can receive the digital input from the CPU. The programmed voltage is available on VPROG pin, which is capable of sourcing or sinking up to 250A. The internal reference accuracy is 1%. 1.9 Dynamically changing DAC code L6996 detects as a transition any change in VID code which duration is larger than 200ns. Then, a timer forces the chip in a 'transition state' for about 100s. In such a state, output protections are disabled and OVP pin goes high. Current limit threshold can be reduced during the transition state duration by using an external mos shorting part of the RILIM resistor. The MOSFET gate is driven by OVP. Reducing current limit threshold prevents from output voltage overshoot/undershoot once the new-programmed voltage has been reached (see waveforms reported below), especially when the droop is not implemented. Note that the reduced threshold must be however high enough to allow the output capacitor to charge/discharge within the transition time. During the transition state duration, zero-cross comparator is disabled and inductor current is allowed to reverse. A negative current limit is introduced. During OFF time, if inductor current is negative and reaches the threshold, low side MOSFET is forced OFF, and remain OFF, allowing negative current to flow across high side body diode, for at least T ON. After then, the low side or high side turns ON again, depending on PWM comparator output. This allows switching frequency to be close to steady state frequency also when the device works in negative current limit protection. Dynamically changing the VID code is useful for portable computers, where the CPU is supply at a higher voltage when the AC-DC adapter is plugged-in, to increase speed. A lower voltage is instead provided when only the battery powers the CPU, to save energy. The dynamic transition is usually made at light load condition, to allow the full current to be available for charging/discharging the output capacitor: Iout ~ 300mA Voutmax ~250mV The current limit threshold should be set high enough to charge/discharge the output capacitor within the transition state duration (see below). If the output voltage changing is higher than 250mV the system can detect an overvoltage or undervoltage that can shut down the device.
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2 APPLICATION INFORMATION
2.1 Demo board description The demoboard shows the device operation in general purpose applications. The evaluation board needs two different supplies; one for the IC section (5V), and another for the conversion section (up to 28V). Output current in excess of 20A can be reached dependently on the MOSFET type. The SW1 is used to start the device (when the supplies are already present) and to select the VID code (i.e. the output voltage). Figure 16. Schematic Diagram
+5V C9 R8 C1 GND VIN R16 VCC VDR C4 OSC BOOT C5 HGATE R9 PHASE PGOOD OVP R10 ILIM R11 Q5 C11 PGOOD OVP R17 LGATE Q3,4,5 D2 C18..C23 GND Q1,2 VOUTSENSE R15 D1 C7 GND C12..C17
+5V +5V R7
L1
R14 VOUT Rout
L6996
PGND GND CS+ CS-
GNDSENSE
SS +5V R2..R6 +5V R1 C10
VFBVFB+ R12
R13 R23 R22 R21 R20 Q6 C6 VPR Q7 Q8
C8
SHDN VID4:0 VID4:0 SHDN
VPROG
U1
+5V +5V U9 R19 +5V U8 +5V U4 +5V U2 +5V U3 +5V C2 +5V C3
+5V R24
GMUXSEL +5V +5V U6 +5V U5
DPSLP
U7 +5V R18 DPSLVR
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2.2 Demoboard Layout Figure 17. PCB Board Layout - Layer one (Top component side) Figure 20. PCB Board Layout - Layer four (Bottom component side)
Figure 18. PCB Board Layout - Layer two (Internal Ground plane)
Figure 21. PCB Board Layout (Component position top view)
Figure 19. PCB Board Layout - Layer three (Internal signal plane)
Figure 22. PCB Board Layout (Component position bottom view)
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L6996
Table 2. PCB Layout guidelines
Goal Low radiation and low magnetic coupling with the adjacent circuitry Suggestion 1) Small switching current loop areas. (For example Placing CIN, high side and Low Side MOSFET, Schottky diode, as close as possible each to others). 2) Controller placed as close as possible to the Power MOSFET. 3) Group the gate drive component (Boot cap and diode together near the IC. Keep the power traces and load connections short and wide. Cs+, CS- traces must be made by Kelvin connection. Also the traces should be separated from the power plane by a ground plane, run parallel. 1) Put the feedback component (like the VP network as close as possible to the IC) 2) The feedback connection (like the FB trace, or CS+/CStraces....) should be route as far as possible from the switching current loops. 3) Make the controller ground connection like in the figure 16.
Don't penalty the efficiency Ensure high accuracy in the current sense system
Reduce the noise effects on IC
3
DESIGN EXAMPLES
3.1 VIN = 20V IOUT = 23A In this design it is considered a low profile demoboard, so a great attention is given to the components height. 3.2 Input capacitor A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC component of this current is quite high and dissipates a considerable amount of power on the ESR of the capacitor: Eq 15
2 Vin ( Vin - Vout ) P CIN = ESR CIN Iou t ----------------------------------------------2 Vin
The IRMS current is given by: Eq 16 Icin rm s = 2 2 Iout ( 1 - ) + ----- ( I L ) 12
Neglecting the last term, the equation reduces to: Eq 17 Icin rm s = Io ut ( 1 - )
PCIN, and also ICINRMS, has a maximum equal to IOUT/2 (@ VIN = 2 x VOUT, that is, 50% duty cycle). The input, therefore, should be selected for a RMS ripple current rating as high as half the respective maximum output current. Electrolytic capacitors are the most used because are the cheapest ones and are available with a wide range of RMS current ratings. The only drawback is that, considering a requested ripple current rating, they are physically larger than other capacitors. Very good tantalum capacitors are coming available, with very low ESR and small size. The only problem is that they occasionally can burn out if subjected to very high current during the charge. So, it is better avoid this type of capacitors for the input filter of the device. In fact, they can be subjected to high surge current when connected to the power supply. If available for the requested value and voltage rating, the ceramic capacitors have usually a higher RMS current rating for a given physical size (due to the very low ESR). From the equation 17 it is found:
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Icinrms = 6.4A Considering 10uF capacitors ceramic, that have ICINRMS =1.5A, 6 pzs. are needed. 3.3 Inductor selection In order to determine the inductor value is necessary considering the maximum output current to decide the inductor current saturation. Once the inductor current saturation is found automatically it is found the inductor value also. The inductor value is important also to determine the duration of the dynamic output voltage transition. In our design it is considered a very low profile inductor. L = 0.6A The saturation current for this choke is 25A 3.4 Output capacitors The output capacitor is chosen by the output voltage static and dynamic accuracy. The static accuracy is related to the output voltage ripple value, while the dynamic accuracy is related to the output current load step. If the static precision is around +/- 4% for the 1.25V output voltage, the output accuracy is 50mV. To determine the ESR value from the output precision is necessary before calculate the ripple current: Eq 18 Vin - Vo Vo I = ---------------------- -------- T sw L Vin
Considering a switching frequency around 270kHz from the equation above the ripple current is around 7A. So the maximum ESR should be: Eq 19 V rip ple 50mV ESR = -------------------- = --------------- = 14m I 3.5 ---2
The dynamic specifications are sometime more relaxed than the static requirements so the ESR value around 7m should be enough. Sometimes can be considered the output capacitor effect also: Eq 20 1 Io ut L Vo ut = --------------------- ------------2 Vo ut C out
2
From the above equation can be calculated the minimum output capacitance value. Considering VOUT = 100mV, COUT > 1600F should be used. Five capacitor of 330F from PANASONIC correspond to the request. To allow the device control loop to properly work, output capacitor ESR zero must be at least ten times smaller than switching frequency. Low ESR tantalum capacitors, which ESR zero is close to 10 kHz, are suitable for output filtering. Output capacitor value COUT and its series resistance, should be large enough and small enough, respectively, to keep output voltage within the accuracy range during a load transient, and to give the device a minimum signal to noise ratio. The current ripple flows through the output capacitor, so the output capacitors should be calculated also to sustain this ripple: the RMS current value is given from Eq21. Eq 21 1 Icout rms = ---------- I L 23
But this is usually a negligible constrain when choosing output capacitor.
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3.5 Power MOSFET and Schottky Diodes Since a 5V bus powers the gate drivers of the device, the use of logic-level MOSFET is highly recommended, especially for high current applications. The breakdown voltage VBRDSS must be greater than VINMAX with a certain margin, so the selection will address 20V or 30V devices (depends on applications). The RDSON can be selected once the allowable power dissipation has been established. By selecting identical Power MOSFET as the main switch and the synchronous rectifier, the total power they dissipate does not depend on the duty cycle. Thus, if PON is this power loss (few percent of the rated output power), the required RDSON (@ 25 C) can be derived from: Eq 22 PO N RD S O N = -----------------------------------------------2 Iou t ( 1 + T )
is the temperature coefficient of RDS(ON) (typically, a = 5*10 -3 C-1 for these low-voltage classes) and T the admitted temperature rise. It is worth noticing, however, that generally the lower RDS ON, the higher is the gate charge QG, which leads to a higher gate drive consumption. In fact, each switching cycle, a charge Q G moves from the input source to ground, resulting in an equivalent drive current: Eq 23 Iq = Q g F SW
The Schottky diode to be placed in parallel to the synchronous rectifier must have a reverse voltage VRRM greater than VINMAX. For this application are selected: two high side MOSFET STS11NF3LL and two STS17NF3LL for the low side section. 3.6 RSENSE selection The droop function consists to change the output voltage changing the output current; at high output current the output voltage is lower than the reference voltage. To implement the droop function, for the high current status, we use the RSENSE resistor in series to the inductor. Since inductor current can be very high, so the resistor must be capable to dissipate high power. Moreover we use the sense resistor to measure the output current for the current limit feature, so the RSENSE value must be very accurate also for temperature variation. To ensure higher temperature stability it could possible to split the RSENSE value. To achieve high efficiency also the RSENSE value must be as low as possible, so the Active voltage droop implemented in L6996 is very useful. For this application it are selected two 3mohms resistors from PANASONIC. 3.7 VP Network Design The voltage-positioning network is selected by the load regulation needed. In this application wit is considered 4mV/A; with a RSENSE resistor around 1.5mohms it can be used a gain around 2.66 and so a rate between R1 and R2 around 1.66 from the Eq6. It can be selected: R1=1.66K R2=1K A capacitor CVP1 is required in parallel with RVP1 to correctly compensate the network response. Its value is given by the following equation: Eq 24 1 1 C VP1 = ESRC OUT C OUT ------------- + ------------- R R
VP1 VP2
where COUT is the output capacitor value. When CVP1 is well chosen, a step decrease of output voltage should be observed, as an effect of a step load increase. Too small or too large C VP1 produces overshoot or undershoot instead of a step waveform.
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With our parameter: CVP1 = 7.8pF No-load offset is obtained by RVP3 and of a current source internally connected to VFB+ pin. Thus: Eq 25 V OUT, I = 0 - V PRO G 1 R VP3 = ---------------------------------------------------- ----------------------R VP2 I O F FSET ------------- + 1 R VP1
where IOFFSET = 5A. The capacitor CVP3 in parallel to RVP3 is a filter which time constant can be the same as in Eq22, so Eq 26 3.8 Input divider The input divider can be selected with the Eq1, Eq2, Eq3 . Choosing a switching frequency around 270kHz it results: OSC = 0.048. R1 = 560K R2 = 27K 3.9 Current limit resistor From the Eq12 it can be set the current limit resistor, for the positive current limit; it results: R10 + R11 = 120K The negative current limit is set by the time available for the negative dynamic transition; a value around 30K for R10 is a match between negative peak current and time to end the dynamic transition (around 80mS). R10=150KW R11=30KW 3.10 Softstart capacitor The soft start capacitor is selected once the soft start time is imposed. It can be consider a soft start time around 1ms. The soft start capacitor is given by: Eq 27 I l im T C SS = ------------------V s s ESRC OUT C OUT C VP3 = -----------------------------------------------R VP 3
Where VSS is the soft start active range and T is the soft stat time. From Eq 28 results: C SS = 10nF.
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Table 3. Component List The component list is shared in two sections: the first for logic and general-purpose component, the second for power section: GENERAL PURPOSE COMPONENTS
Part name R1, R2, R3, R4, R5, R6, R7, R9, R18, R19, R24 R8 R10 R11 R12 R13 R15 Value 33k 47k 120k 30k 1.66k 1k 560k Input resistor divider (to set the switching frequency) IMVPII resistor network Voltage positioning resistors Current limit resistors (to set the current limit) Part number Manufacturer Notes
R16 R20 R21 R22 R23 C1 C2, C3 C4 C5 C6 C7 C8 C9 C10 C11 U2, U6, U8 U9, U7 U3,U4,U5 D1 Q5,Q6,Q7,Q8 SW1, SW2
27k 130k 39k 36k 270k 47F 100nF 220nF 220nF 10nF 220nF 6.8nF 47pF 10nF 47pF Or gate Inverter gate Nor gate BAT54A BSS131 DIP SWITCH NC7SZ32M5 NC7SZ04P5 NC7SZ02P5 BAT54A Q62702-S565 FAIRCHILD FAIRCHILD FAIRCHILD PHILIPS INFINEON *1 Logic network Voltage positioning capacitor Tantalum/SP
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POWER SECTION
SENSE RESISTOR Part name R14, R17 Value 3m Part number ERJM1WSF3M0U Manufacturer PANASONIC Notes 1%
It is important, for this component, to keep in mind three factor: it must be able to dissipate high power. Again its variation with the temperature must be small and the precision must be high to ensure high precision with the ST voltage droop function.
INPUT CAPACITOR Part name C12,C13,C14,C15,C16,C17 Value 10F 10F 10F 10F 10F 10F Part number ECJ5YB1E106M ECJ5YF1E106M C34Y5U1E106ZTE12 GMK325F106ZH TMK325F106ZH TMK432BJ106MM Manufacturer PANASONIC PANASONIC TOKIN TAIYO-YUDEN TAIYO-YUDEN TAIYO-YUDEN Notes 25V ceramic 25V ceramic 25V ceramic 35V ceramic 25V ceramic 25V ceramic
For this components can be useful control the temperature coefficient and the equivalent serie resistor and the voltage rated.
OUTPUT CAPACITOR Part name C18,C19,C20,C21,C22,C23 C18,C19,C20,C21,C22 Value 270F 330F Part number EEFUE0D271R EEFUE0D271R Manufacturer PANASONIC PANASONIC Notes 2V 2V
For this components can be useful control the temperature coefficient and the equivalent series resistor and the voltage rated.
INDUCTOR Part name L1 Value 0.6F 0.6F 0.6F Part number ETQP6F0R6BFA A959AS-R60N CEP12D38H-0R6 Manufacturer PANASONIC TOKO SUMIDA Notes
For the inductor important factors are the saturation current and the equivalent series resistor (for the efficiency improvements)
POWER MOS Part name High side Q1, Q2 Low Side Q3, Q4 STS17NH3LL STS25NH3LL STS17NH3LL STS25NH3LL STMicroelectronics STMicroelectronics Q5 N.M . STS11NF3LL STSJ25NF3LL STS11F3LL STSJ25NF3LL STMicroelectronics STMicroelectronics Value Part number Manufacturer Notes
Note N.M.=Not Mounted. For the MOSFET choose is important to know the input voltage and output voltage. The MOSFET must able
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dissipate high power (for switching losses or conduction losses).
POWER DIODES Part name D2 Value STPS2L25U Part number STPS2L25U Manufacturer STMICROELECTRONICS Notes 25V
This component must have low forward voltage and must have high reverse voltage (at least equal at the input voltage).
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mm DIM. MIN. A A1 A2 b c D E E1 e L L1 k 0.45 4.30 0.05 0.80 0.19 0.09 7.70 7.80 6.40 4.40 0.65 0.60 1.00 0 min., 8 max. 0.75 0.018 4.50 0.170 1.00 TYP. MAX. 1.20 0.15 1.05 0.30 0.20 7.90 0.002 0.031 0.007 0.003 0.303 MIN.
inch TYP. MAX. 0.047 0.006 0.039 0.041 0.012 0.008 0.307 0.252 0.173 0.025 0.024 0.039 0.030 0.177 0.311
OUTLINE AND MECHANICAL DATA
TSSOP24
Thin Shrink Small Outline Package
7100777 (JEDEC MO-153-AD)
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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